Renesas SH7781 - Manual (Page 292)

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 262 of 1658
REJ09B0261-0100
(2) IL Memory
In order to allocate instructions in the IL memory, write an instruction to the IL memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (IL memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
(3) U Memory
In order to allocate instructions in the U memory, write an instruction to the U memory, execute
the following sequence, then branch to the rewritten instruction.
• SYNCO
• ICBI @Rn
In this case, the target for the ICBI instruction can be any address (U memory address may be
possible) within the range where no address error exception occurs, and cache hit/miss is possible.
9.5.4 Sleep Mode
(1) OL Memory, IL Memory
The SuperHyway bus master module, such as DMAC, cannot access OL memory and IL memory
in sleep mode.
(2) U Memory
The SuperHyway bus master module, such as DMAC, can access U memory in sleep mode.
9.6 Note on Using 32-Bit Address Extended Mode
In 32-bit address extended mode, L0SADR fields in LSA0, L1SADR fields in LSA1, L0DADR
fields in LDA0, and L1DADR fields in LDA1 are extended from 19-bit [28:10] to 22-bit [31:10].