Renesas SH7781 - Manual (Page 196)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 166 of 1658
REJ09B0261-0100
1: Cacheable
When the control register area is mapped, this bit must be cleared to 0.
• D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed
1: Write has been performed
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
31
• 1-Kbyte page
10 9 0
Virtual address
31
• 4-Kbyte page
12 11 0
Virtual address
31
• 64-Kbyte page
16 15 0
Virtual address
31
• 1-Mbyte page
20 19 0
Virtual address
VPN Offset
VPN Offset
VPN Offset
VPN Offset
28 10 9 0
Physical address
28 12 11 0
Physical address
28 16 15 0
Physical address
28 20 19 0
Physical address
PPN Offset
PPN Offset
PPN Offset
PPN Offset
Figure 7.7 Relationship between Page Size and Address Format (TLB Compatible Mode)