Renesas SH7781 - Manual (Page 409)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 379 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
19
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16 RDH 111 R/W
RD Hold Cycle (RD Negation–CSn Negation Delay
Cycle)
These bits specify the number of cycles to be inserted
as the time from
RD negation to CSn negation. (Only
valid when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted (0 cycle delayed)
001: 1 cycle inserted (1 cycle delayed)
010: 2 cycles inserted (2 cycles delayed)
011: 3 cycles inserted (3 cycles delayed)
100: 4 cycles inserted (4 cycles delayed)
101: 5 cycles inserted (5 cycles delayed)
110: 6 cycles inserted (6 cycles delayed)
111: 7 cycles inserted (7 cycles delayed)
15
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 WTS 111 R/W
WE Setup Cycle (CSn Assertion–WE Assertion Delay
Cycle)
These bits specify the number of cycles to be inserted
as the time from
CSn assertion to WE assertion. (Only
valid when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted (0.5 cycle delayed)
001: 1 cycle inserted (1.5 cycles delayed)
010: 2 cycles inserted (2.5 cycles delayed)
011: 3 cycles inserted (3.5 cycles delayed)
100: 4 cycles inserted (4.5 cycles delayed)
101: 5 cycles inserted (5.5 cycles delayed)
110: 6 cycles inserted (6.5 cycles delayed)
111: 7 cycles inserted (7.5 cycles delayed)