Renesas SH7781 - Manual (Page 771)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 741 of 1658
REJ09B0261-0100
15.4.1 Frequency Control Register 0 (FRQCR0)
FRQCR0 is a 32-bit readable and partially writable register that executes a sequence for changing
the frequency of each clock. After the sequence is executed, FRQCR0 is automatically cleared to
0. FRQCR0 can only be accessed in longwords.
To write to FRQCR0, set the code value (H'CF) in the upper byte and use the longword. No other
code values can be written. The code value is always read as 0.
FRQCR0 is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Code value (H'CF)
R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FRQE
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 24
⎯
All 0 R/W Code value (H'CF)
These bits are always read as 0. The write value
should always be H'CF.
23 to 1
⎯ All
0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 FRQE 0 R/W Frequency Change Sequence Enabled
Enables the execution of a sequence that changes the
frequency of each clock according to the value set in
FRQCR1. After executing the sequence, this bit is
automatically cleared to 0.
0: Execution of a sequence that changes the frequency
is disabled.
1: Execution of a sequence that changes the frequency
is enabled.
Note: Some division ratio settings are prohibited. When
a value that is not shown in Tables 15.8 to 15.11
is set in FRQCR1, do not set 1 in FRQE.