Renesas SH7781 - Manual (Page 1377)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1347 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
25 CDSRC 0 R/W Data Buffer Specification
Specifies the data buffer to be read from or written to in
the data stage* in command access mode.
0: Specifies FLDATAR as the data buffer.
1: Specifies FLDTFIFO as the data buffer.
24 DOSR 0 R/W Status Read Check
Specifies whether the status read is performed after the
second command has been issued in command access
mode.
0: Performs no status read
1: Performs status read
23, 22 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
21 SELRW 0 R/W Data Read/Write Specification
Specifies whether the direction is read or write in data
stage.
0: Read
1: Write
20 DOADR 0 R/W Address Stage Execution Specification
Specifies whether the address stage* is executed in
command access mode.
0: Performs no address stage
1: Performs address stage
19, 18 ADRCNT
[1:0] 00 R/W Address Issue Byte Count Specification
Specify the number of bytes for the address data to be
issued in address stage*.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
17 DOCMD2 0 R/W Second Command Stage* Execution Specification
Specifies whether the second command stage* is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage