Renesas SH7781 - Manual (Page 294)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 264 of 1658
REJ09B0261-0100
Figure 10.1 shows a block diagram of the INTC.
Input control
Priority
determination
for external
interrupts
(levels 1 to 15)
Priority
determination
for on-chip
peripheral
module
interrupts
(levels 2 to 31)
Bus interface
WDT
H-UDI
DMAC
PCIC
DU
GDTA
GPIO interrupts
Interrupt request
USERIMASK.UIMASK
Compar
ator
Bus interface
Compar
ator
CPU
Interrupt
acceptance
INTPRI
SR.IMASK
ICR0, 1
INT2PRI0 to
INT2PRI9
INT2GPIC
Other peripheral
modules*
On-chip
modules
Interrupt request
Interrupt request
Interrupt request
Interrupt request
Interrupt request
Interrupt request
NMI
NMI
IRQOUT
IRQ/ IRL7 to
IRQ/ IRL4 and
GPIO port
L4 to L1 are
multiplexed
IRQ/ IRL7 to
IRQ/ IRL0
GPIO Port
E5 to E0
H4 to H1
L7, L6
IRL
IRQ 8
12
P
er
ipher
al b
us
Note: * Other peripheral modules that can output interrupts are TMU, SCIF, HAC, SIOF, HSPI, MMCIF, SSI, and FLCTL.
Legend:
DMAC:
DU:
FLCTL:
GDTA:
HAC:
HSPI:
H-UDI:
ICR0, ICR1:
INTPRI:
INT2PRI0 to
INT2PRI9:
INT2GPIC: Direct Memory Access Controller
Display Unit
NAND Flash Memory Controller
Graphics Data Translation Accelerator
Audio Codec Interface
Serial Peripheral Interface
User Debugging Interface
Interrupt Control Registers 0, 1
Interrupt Priority Level Register
Interrupt Priority Registers 0 to 9
GPIO Interrupt Set Register
MMCIF:
PCIC:
SCIF:
SIOF:
SR.IMASK:
SSI:
TMU:
USERIMASK.
UIMASK:
WDT: Multimedia Card Interface
PCI Controller
Serial Communication Interface with FIFO
Synchronous Serial I/O with FIFO
IMASK bit in Status Register
Serial Sound Interface
Timer Unit
UIMASK bit in User Interrupt Mask Level Register
Watch Dog Timer
Figure 10.1 Block Diagram of INTC