Renesas SH7781 - Manual (Page 541)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 511 of 1658
REJ09B0261-0100
By writing to this register, the DDR2-SDRAM address and bank address pins can be directly
manipulated to set the mode and extended mode registers. When this register is written, the mode
register setting (MRS)/extended mode register setting (EMRS) command is issued for the DDR2-
SDRAM. Upon command execution, settings should be made such that the burst length is 4, the
mode is sequential access mode, and the additive latency (AL) is 0, the DQS is enable, and the
RDQS is disable. Further, settings should be made such that the CAS latency (CL)/write recovery
(WR) is equal to the corresponding bits in SDRAM timing registers 0 and 1 (DBTR0 and
DBTR1).