Renesas SH7781 - Manual (Page 830)

18. Timer Unit (TMU)
Rev.1.00 Jan. 10, 2008 Page 800 of 1658
REJ09B0261-0100
Figure 18.1 shows a block diagram of the TMU.
Channel 0, 1
Channel 2
Channel 3, 4, 5
TCR
TSTR0
TSTR1
Clock
controller
TCLK
controller
TCLK
TUNI0
TUNI1
TUNI2
ICPI2
Pck/4
Pck/16
Pck/64
TUNI3
TUNI4
TUNI5
Prescaler
To each
channel
Interrupt
controller
Clock
controller
Interrupt
controller
Clock
controller
Interrupt
controller
TCOR
TCNT
TCR
TCOR
TCNT
TCR
Peripheral
bus
TCOR
TCNT
TCPR2
Bus interf
ace
Legend:
TCNT:
TCOR:
TCPR2:
TCR:
TSTR0, TSTR1: Timer counter
Timer constant register
Input capture register 2 (channel 2 only)
Timer control register
Timer start register
Figure 18.1 Block Diagram of TMU