Renesas SH7781 - Manual (Page 584)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 554 of 1658
REJ09B0261-0100
13.2 Input/Output Pins
Table 13.1 shows the pin configuration of the PCIC.
Table 13.1 Signal Descriptions
Signal Name
PCI Standard
Signal I/O
Description
D32/AD0/DR0 to
D37/AD5/DR5,
D38/AD6/DG0 to
D43/AD11/DG5,
D44/AD12/DB0 to
D49/AD17/DB5,
D50/AD18 to
D63/AD31 AD[31:0] TRI PCI Address/Data Bus
Address and data buses are multiplexed. In each bus
transaction, an address phase is followed by one or
more data phases.
WE7/CBE3 to
WE4/CBE0
C/
BE[3:0]
TRI PCI Command/Byte Enable
Commands and byte enable are multiplexed. These
signals indicate the type of command and byte enable
during the address phase and the data phases
respectively.
PAR PAR TRI PCI Parity
Generates/checks even parity between AD[31:0] to
C/
BE[3:0].
PCICLK/
DCLKIN CLK IN PCI Clock
Provides timing for all transactions on the PCI bus.
PCIFRAME/
VSYNC
FRAME
STRI PCI Frame
Driven by the current initiator, and indicates the start
and duration of a transaction.
TRDY/DISP TRDY
STRI PCI Target Ready
Driven by the selected target, and indicates the target
is ready to start and maintain a transaction.
IRDY/HSYNC IRDY
STRI PCI Initiator Ready
Driven by the current bus master. During writing,
indicates that valid data is present on the AD [31:0]
lines. During reading, indicates that the master is ready
to accept data.
STOP/CDE STOP
STRI PCI Stop
Driven by the selected target drives to stop the current
transaction.