Renesas SH7781 User Manual

Page 415

11. Local Bus State Controller (LBSC)

Rev.1.00 Jan. 10, 2008 Page 385 of 1658

REJ09B0261-0100

Bit Bit

Name

Initial
Value R/W Description

14 to 12 TEDA

000

R/W

OE/WE Assert Delay A
These bits set the delay time from address output to

OE/WE assertion when the first half area is accessed
with the connected PCMCIA interface.

000: No wait cycle inserted

001: 1 wait cycle inserted

010: 2 wait cycles inserted

011: 3 wait cycles inserted

100: 6 wait cycles inserted

101: 9 wait cycles inserted

110: 12 wait cycles inserted

111: 15 wait cycles inserted

⎯ 0

Reserved

This bit is always read as 0. The write value should
always be 0.

10 to 8

TEDB

000

R/W

OE/WE Assert Delay B
These bits set the delay time from address output to

OE/WE assertion when the second half area is
accessed with the connected PCMCIA interface.