Renesas SH7781 - Manual (Page 746)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 716 of 1658
REJ09B0261-0100
DMA CH0
Cycle steal
CH0 transfer source
(a) CH0: Cycle steal mode
CH1: Cycle steal mode
Priority: CH0 > CH1
CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH1 CPU
DMA CH1
Cycle steal
CH1 transfer source
DMA CH0
Cycle steal
CH1 transfer source
CH0 transfer source
CPU DMA CH0 DMA CH0 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH0
DMA CH0
Cycle steal
CPU
DMA CH0 and CH1
Burst mode
DMA CH1
Cycle steal
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH1 DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH1
DMA CH1
Cycle steal
CPU
DMA CH0
Cycle steal
DMA CH1
Cycle steal
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH1 DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH1
DMA CH1
Cycle steal
CPU
DMA CH0
Burst mode
DMA CH1
Burst mode
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1
DMA CH1
Burst mode
CPU
DMA CH0 and CH1
Burst mode
DMA CH0
Burst mode
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH DMA CH0 DMA CH1
DMA CH1
Cycle steal
CPU
DMA CH0
Burst mode
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH1
DMA CH1
Burst mode
CPU
DMA CH1
Burst mode
CH1 transfer source
CH0 transfer source
CPU DMA CH1 DMA CH1 DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH1
DMA CH1
Burst mode
CPU
DMA CH0
Burst mode
(b) CH0: Cycle steal mode
CH1: Cycle steal mode
Priority: CH0 > CH1
(d) CH0: Cycle steal mode
CH1: Burst mode
Priority: CH0 > CH1
(e) CH0: Burst mode
CH1: Cycle steal mode
Priority: CH0 > CH1
(f) CH0: Burst mode
CH1: Cycle steal mode
Priority: CH0 > CH1
(g) CH0: Burst mode
CH1: Burst mode
Priority: CH0 > CH1
(h) CH0: Burst mode
CH1: Burst mode
Priority: CH0 > CH1
(c) CH0: Cycle steal mode
CH1: Burst mode
Priority: CH0 > CH1
Figure 14.10 Bus Mode and Channel Priority in Priority Fixed Mode