Renesas SH7781 - Manual (Page 536)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 506 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
2 to 0 FREQ2 to
FREQ0 000 R/W Frequency Setting Bits
These bits set the operating frequency of the data bus
in the DDR2-SDRAM.
000: up to 300 MHz (DDR2-600)
001: Reserved
010: 200 MHz (DDR2-400)
100 to 111: Setting prohibited. (If specified, correct
operation cannot be guaranteed.)
Note: This register is used for initialization, when canceling self-refresh, and when canceling
power supply backup.
For details, refer to section 12.5.3, Initialization Sequence, section 12.5.4, Self-Refresh
Operation, and (2) Recovery from SDRAM Power Supply Backup Mode in section 12.5.10,
DDR2-SDRAM Power Supply Backup Function.