Renesas SH7781 - Manual (Page 1135)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1105 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
7 TXDIZ 0 R/W SIOF_TXD Pin Output when Transmission is Invalid*
0: High output when invalid
1: High-impedance state when invalid
Note: Transmission is invalid when transmission is
disabled, or when a slot that is not assigned as
transmit data or control data is being
transmitted.
6 RCIM 0 R/W Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
SIRCR change.
1: Sets the RCRDY bit in SISTR each time when
SIRCR receives the control data.
5 SYNCAC 0 R/W SIOF_SYNC Pin Polarity
This bit is valid when the SIOF_SYNC signal is output
as synchronous pulse.
0: Active-high
1: Active-low
4 SYNCDL 0 R/W Data Pin Bit Delay for SIOF_SYNC Pin
This bit is valid when the SIOF_SYNC signal is output
as synchronous pulse. In slave mode, specify one-bit
delay.
0: No bit delay
1: 1-bit delay
3 to 0
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Table 22.4 shows the operation in each transfer mode.
Table 22.4 Operation in Each Transfer Mode
Transfer Mode Master/Slave SIOF_SYNC Bit Delay Control Data Method*
Slave mode 1 Slave Synchronous pulse Slot position
Slave mode 2 Slave Synchronous pulse Secondary FS
Master mode 1 Master Synchronous pulse
SYNCDL bit
Slot position
Master mode 2 Master L/R No Not supported
Note: * The control data method is valid when the FL bits are set to 1xxx. (x: don't care.)
For details, see section 22.4.5, Control Data Interface.