Renesas SH7781 - Manual (Page 1485)

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1455 of 1658
REJ09B0261-0100
29.2 Register Descriptions
The UBC has the following registers.
Table 29.1 Register Configuration
Name Abbreviation R/W P4 Address*
Area 7
Address* Access
Size
Match condition setting
register 0 CBR0 R/W H'FF200000 H'1F200000 32
Match operation setting
register 0 CRR0 R/W H'FF200004 H'1F200004 32
Match address setting
register 0 CAR0 R/W H'FF200008 H'1F200008 32
Match address mask setting
register 0 CAMR0 R/W H'FF20000C H'1F20000C 32
Match condition setting
register 1 CBR1 R/W H'FF200020 H'1F200020 32
Match operation setting
register 1 CRR1 R/W H'FF200024 H'1F200024 32
Match address setting
register 1 CAR1 R/W H'FF200028 H'1F200028 32
Match address mask setting
register 1 CAMR1 R/W H'FF20002C H'1F20002C 32
Match data setting register 1 CDR1 R/W H'FF200030 H'1F200030 32
Match data mask setting
register 1 CDMR1 R/W H'FF200034 H'1F200034 32
Execution count break
register 1 CETR1 R/W H'FF200038 H'1F200038 32
Channel match flag register CCMFR R/W H'FF200600 H'1F200600 32
Break control register CBCR R/W H'FF200620 H'1F200620 32
Note: * P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.