Renesas SH7781 User Manual
Page 599
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 569 of 1658
REJ09B0261-0100
(6)
PCI Program Interface Register (PCIPIF)
This field is the programming interface for the class code of the IDE controller. For details of the
code value, see appendix D in PCI Local Bus Specification Revision 2.2.
R
R
R
R
R
R
R
R
PCI R/W:
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
OMP
PIP
OMS
PIS
—
—
—
MIDED
R/W
R/W
R/W
R/W
R
R
R
R/W
Bit:
Initial value:
SH R/W:
Bit Bit
Name
Initial
Value R/W
Description
7 MIDED
0
SH:
R/W
PCI: R
PCI Master IDE Device
Specifies the PCI master IDE device.
0: PCI slave IDE device
1: PCI master IDE device
If this bit is written during register initialization
(PCICR.CFINT
= 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT
= 1).
6 to 4
⎯
All 0
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 PIS 0
SH:
R/W
PCI: R
PCI Programmable Indicator (Secondary)
If this bit is written during register initialization
(PCICR.CFINT
= 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT
= 1).
2 OMS
0
SH:
R/W
PCI: R
PCI Operating Mode (Secondary)
If this bit is written during register initialization
(PCICR.CFINT
= 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT
= 1).
1 PIP 0
SH:
R/W
PCI: R
PCI Programmable Indicator (Primary)
If this bit is written during register initialization
(PCICR.CFINT
= 0) in the PCIC, the value of this bit is
updated. The value is not updated after initialization
(PCICR.CFINT
= 1).