Renesas SH7781 - Manual (Page 17)

Rev.1.00 Jan. 10, 2008 Page xvii of xxx
REJ09B0261-0100
14.4.2 Channel Priority.................................................................................................. 706
14.4.3 DMA Transfer Types.......................................................................................... 709
14.4.4 DMA Transfer Flow ........................................................................................... 717
14.4.5 Repeat Mode Transfer ........................................................................................ 719
14.4.6 Reload Mode Transfer ........................................................................................ 720
14.4.7 DREQ Pin Sampling Timing .............................................................................. 721
14.5 DMAC Interrupt Sources ................................................................................................... 729
14.6 Usage Notes ....................................................................................................................... 730
14.6.1 Stopping Modules and Changing Frequency ...................................................... 730
14.6.2 Address Error...................................................................................................... 730
14.6.3 NMI Interrupt...................................................................................................... 730
14.6.4 Burst Mode Transfer........................................................................................... 730
14.6.5 Divided-Up DACK Output ................................................................................. 730
14.6.6 DACK/DREQ Setting......................................................................................... 731
Section 15 Clock Pulse Generator (CPG) ..................................................................... 733
15.1 Features.............................................................................................................................. 733
15.2 Input/Output Pins ............................................................................................................... 736
15.3 Clock Operating Modes ..................................................................................................... 737
15.4 Register Descriptions ......................................................................................................... 739
15.4.1 Frequency Control Register 0 (FRQCR0) .......................................................... 741
15.4.2 Frequency Control Register 1 (FRQCR1) .......................................................... 742
15.4.3 Frequency Display Register 1 (FRQMR1) ......................................................... 745
15.4.4 PLL Control Register (PLLCR).......................................................................... 747
15.5 Calculating the Frequency ................................................................................................. 748
15.6 How to Change the Frequency........................................................................................... 749
15.6.1 Changing the Frequency of Clocks Other than the Bus Clock ........................... 749
15.6.2 Changing the Bus Clock Frequency ................................................................... 749
15.7 Notes on Designing Board ................................................................................................. 756
Section 16 Watchdog Timer and Reset (WDT) ........................................................... 759
16.1 Features.............................................................................................................................. 759
16.2 Input/Output Pins ............................................................................................................... 761
16.3 Register Descriptions ......................................................................................................... 762
16.3.1 Watchdog Timer Stop Time Register (WDTST) ................................................ 763
16.3.2 Watchdog Timer Control/Status Register (WDTCSR)....................................... 764
16.3.3 Watchdog Timer Base Stop Time Register (WDTBST)..................................... 766
16.3.4 Watchdog Timer Counter (WDTCNT)............................................................... 767
16.3.5 Watchdog Timer Base Counter (WDTBCNT) ................................................... 768
16.4 Operation ........................................................................................................................... 769