Renesas SH7781 - Manual (Page 713)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 683 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Descriptions
21
⎯ 0 R
Reserved
This bit is always read as 0. The write value should
always be 0.
20 TS2 0 R/W DMA Transfer Size Specification
Specifies the DMA transfer size with TS1 and TS0.
When the transfer source or transfer destination is a
register in an on-chip peripheral module register that
the access size is specified, the transfer data size for
the register should be the same as the access size. For
the address set to SAR or DAR as transfer source or
transfer destination, the transfer data size should be the
same as the address boundary.
TS2, TS1, TS0
000: Byte units
001: Word (2-byte) units
010: Longword (4-byte) units
011: 16-byte units
100: 32-byte units
Other than above: Setting prohibited