Renesas SH7781 - Manual (Page 249)

8. Caches
Rev.1.00 Jan. 10, 2008 Page 219 of 1658
REJ09B0261-0100
8.2.3 Queue Address Control Register 1 (QACR1)
QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit:
Initial value:
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R/W R/W R/W R R
R/W:
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AREA1
Bit Bit Name
Initial
Value R/W
Description
31 to 5
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
4 to 2 AREA1 Undefined R/W When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ1.
1, 0
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.