Renesas SH7781 - Manual (Page 803)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 773 of 1658
REJ09B0261-0100
WDTBCNT is an 18-bit counter that is incremented by the peripheral clock. If the period of
peripheral clock Pck is represented as tPck (ns), the overflow time of WDTBCNT is expressed as
follows.
2 18 [bit]
×
tPck [ns] = 0.262
×
tPck [ms]
WDTCNT is a 12-bit counter that is incremented each time WDTBCNT overflows. The time until
WDTCNT overflows becomes maximum when 0 is written to all the bits in WDTST. If the period
of peripheral clock Pck is represented as tPck (ns), the maximum overflow time of WDTCNT is
expressed as follows.
2 12 [bit]
Ч (
0.262
Ч
tPck) [ms] = 1.073
×
tPck [s]
The time until WDTCNT overflows becomes minimum when H'5A00 0001 is written to WDTST.
In this case, the overflow time is equal to that of WDTBCNT.
For example, if the peripheral clock frequency is 50 MHz, tPck is 20 ns and the overflow times are
as follows.
Overflow time of WDTBCNT: 0.262
×
20 = 5.24 [ms]
Maximum overflow time of WDTCNT: 1.073
×
20 = 21.46 [s]
16.4.5 Clearing WDT Counters
Setting the overflow value in WDTBST clears WDTBCNT to 0, and setting the overflow value in
WDTST clears WDTCNT to 0.