Renesas SH7781 - Manual (Page 1489)

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1459 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
7, 6 CD All 0 R/W Bus Select
Specifies the bus to be included in the match conditions.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Operand bus for operand access
Others: Reserved (setting prohibited)
5, 4 ID All 0 R/W Instruction Fetch/Operand Access Select
Specifies the instruction fetch cycle or operand access
cycle as the match condition.
00: Instruction fetch cycle or operand access cycle
01: Instruction fetch cycle
10: Operand access cycle
11: Instruction fetch cycle or operand access cycle
3 — 0 R Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
2, 1 RW All 0 R/W Bus Command Select
Specifies the read/write cycle as the match condition.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Read cycle or write cycle
01: Read cycle
10: Write cycle
11: Read cycle or write cycle
0 CE 0 R/W Channel Enable
Validates/invalidates the channel. If this bit is 0, all the
other bits of this register are invalid.
0: Invalidates the channel.
1: Validates the channel.
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
size.
2. If the quadword access is specified and the data value is included in the match
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and the match data mask setting
register.