Renesas SH7781 - Manual (Page 596)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 566 of 1658
REJ09B0261-0100
(4) PCI Status Register (PCISTATUS)
PCISTATUS is used to record status information for events related to the PCI bus. The reserved
bits are read-only bits that are read as 0.
Reading from this register is normally performed. During writing, the write clear bit can be reset,
but it cannot be set (R/WC in the figure below). Write 1 to the bit to be cleared. For example, to
clear bit 14 so that other bits will not be affected, write the B'0100 0000 0000 0000 to this register.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
⎯ ⎯ ⎯ ⎯
CL 66C
⎯
FBBC MDPE DEVSEL STA RTA RMA DPE SSE
0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0
R R R R R R/W R R R/WC R R R/WC R/WC R/WC R/WC R/WC
Bit:
Initial value:
SH R/W:
R R R R R R R R R/WC R R R/WC R/WC R/WC R/WC R/WC PCI R/W:
Bit Bit Name
Initial
Value R/W
Description
15 DPE 0 SH: R/WC
PCI: R/WC
Parity Error Detect Status
Indicates that a parity error was detected in read data
when the PCIC is a master, or in write data when the
PCIC is a target. This bit is set regardless of the value
of parity error response bit.
0: Device did not detect parity error.
1: Device detected parity error.
14 SSE 0 SH: R/WC
PCI: R/WC
System Error Output Status
Indicates that the PCIC asserted
SERR.
0:
SERR was asserted
1:
SERR was asserted (the value is retained until this
bit is cleared)
13 RMA 0 SH: R/WC
PCI: R/WC
Master Abort Receive Status
This bit indicates that a transaction was completed by
master abort when the PCIC is a master.
0: Transaction is not completed by master abort
1: The bus master detected completion of transaction
by master abort. Master abort is not set in special
cycles.