Renesas SH7781 - Manual (Page 484)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 454 of 1658
REJ09B0261-0100
Table 11.20 Register Settings for Divided-Up
DACKn Output in DMA1 Transfer Using the
PCMCIA Interface
Not Divided Divided
Bus Width
[Bit]
Access Size Bus Cycle Number
IWRRD, IWRRS, or
IWW in CSnBCR IWRRD, IWRRS, or
IWW in CSnBCR
Byte 1
⎯ Undividable
Word 2
⎯ Undividable∗ 1
Longword 4
⎯ Undividable∗ 1
16 bytes 16 B'000 B'111 to B'001
∗ 2
8
32 bytes 32
⎯ Undividable∗ 1
16 Byte 1
⎯ Undividable
Word 1
⎯ Undividable
Longword 2
⎯ Undividable∗ 1
16 bytes 8 B'000 B'111 to B'001
∗ 2
32 bytes 16
⎯ Undividable∗ 1
Notes: "
⎯" means an arbitrary setting value. When transfer is done in a single bus cycle, DACKn
is not divided up because
DACKn is output once in DMA1 transfer.
1. Multiple bus cycles are generated, however,
DACKn cannot be divided.
2. Can be divided only in longword units.