Renesas SH7781 - Manual (Page 638)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 608 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
11 MBTOI 0 SH: R/WC
PCI: R
Master Bus Time-Out Interrupt
An interrupt is detected when
IRDY is not asserted
within 8 clock cycles during data transfer.
0: A master bus timeout interrupt was not generated
1: A master bus timeout interrupt was generated
10 to 4
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 TAI 0 SH: R/WC
PCI: R
Target-Abort Interrupt
Indicates that a transaction was terminated by a target
abort when a device other than the PCIC is a bus
master.
0: A target abort interrupt was not generated
1: A target abort interrupt was generated
2 MAI 0 SH: R/WC
PCI: R
Master-Abort Interrupt
Indicates that a transaction was terminated by a
master abort when a device other than the PCIC is a
bus master.
0: A master abort interrupt was not generated
1: A master abort interrupt was generated
1 RDPEI 0 SH: R/WC
PCI: R
Read Parity Error Interrupt
PERR assertion was detected during data read when
a device other than the PCIC is a bus master.
0: A read parity error interrupt was not generated
1: A read parity error interrupt was generated
0 WDPEI 0 SH: R/WC
PCI: R
Write Parity Error Interrupt
PERR assertion was detected during data write when
a device other than the PCIC is a bus master.
0: A write data parity error interrupt was not generated
1: A write data parity error interrupt was generated