Renesas SH7781 - Manual (Page 1210)

24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1180 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
6 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
5 RD_CONTI 0 R/W Read Continue
Read data reception is resumed when 1 is written while
the sequence has been halted by FIFO full or
termination of block reading in multiple block read.
This bit is cleared to 0 automatically when 1 is written
and the MMCIF received the RD_CONTI command.
Write enabled period: While read data reception is
halted
Write of 0: Operation is not affected.
Write of 1: Resumes read data reception.
Note: Do not write to this bit out of the write enable
period.
4 DATAEN 0 R/W Data Enable
Starts a write data transmission by a command with
write data. This bit is cleared automatically when 1 is
written and the MMCIF received the DATAEN
command. Resumes write data transmission while the
sequence has been halted by FIFO empty or
termination of block writing in multiple block write.
Write enabled period: (1) after receiving a response to a
command with write data, (2) while sequence is halted
by FIFO empty, (3) when one block writing in multiple
block write is terminated.
Write of 0: Operation is not affected.
Write of 1: Starts or resumes write data transmission.
Note: Do not write to this bit out of the write enable
period.
3 to 0 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.