Renesas SH7781 - Manual (Page 810)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 780 of 1658
REJ09B0261-0100
(2) Manual Reset Caused by Watchdog Timer Overflow in Sleep Mode
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
WDT reset setup time WDT manual reset holding time
WDT overflow
signal
CLKOUT
output
STATUS[1:0]
output
HH (reset) LL (normal) HL (sleep)
EXTAL
input
CLKOUTENB
output
MRESETOUT
output
Figure 16.9 STATUS Output by Manual Reset Caused by WDT Overflow
in Sleep Mode