Renesas SH7781 User Manual
Page 224
7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 194 of 1658
REJ09B0261-0100
(2)
ITLB Data Array 2
The ITLB data array is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. Access
to data array 2 requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and EPR and ESZ to be written to data array 2 are specified in the
data field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2 and the entry is
specified by bits [9:8].
In the data field, bits [13], [11], [10], and [8] indicate EPR[5], [3], [2], and [0], and bits [7:4]
indicate ESZ, respectively.
The following two kinds of operation can be applied to ITLB data array 2:
1. ITLB data array 2 read
EPR and ESZ are read into the data field from the ITLB entry corresponding to the entry set in
the address field.
2. ITLB data array 2 write
EPR and ESZ specified in the data field are written to the ITLB entry corresponding to the
entry set in the address field.
Legend:
E:
EPR:
ESZ:
*:
Entry
Protection key data
Page size bits
Don't care
EPR[5]
EPR[3]
EPR[0]
EPR[2]
Address field
Data field
Reserved bits
(write value should be 0,
and read value is undefined)
31
0
ESZ
10 9 8
13
14
1211
7
2 1
4 3
31
0
0
0
1 1 1 1 0 0 1 1 1
E
23 22
8 7
10 9
* * * * * *
* *
*
*
*
*
* * * * * * *
:
Figure 7.21 Memory-Mapped ITLB Data Array 2 (TLB Extended Mode)