Renesas SH7781 - Manual (Page 322)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 292 of 1658
REJ09B0261-0100
(9) Interrupt Mask Clear Register 1 (INTMSKCLR1)
INTMSKCLR1 is a 32-bit write-only register that clears the mask settings for the IRL interrupt
requests. Undefined values are read from this register.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IC10 IC11
R R R R R R R R R R R R R R R/W R/W
Bit:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IC10 0 R/W Clears masking of
IRL3 to
IRL0 interrupt sources
when
IRL3 to IRL0 operate
as an encoded interrupt
input.
30 IC11 0 R/W Clears masking of
IRL7 to
IRL4 interrupt sources
when
IRL7 to IRL4 operate
as an encoded interrupt
input.
[When read]
Undefined values are read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
29 to 0
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.