Renesas SH7781 - Manual (Page 1303)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1273 of 1658
REJ09B0261-0100
25.3.3 Command/Status Data Register (HACCSDR)
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the
command data to HACCSDR and set the ST bit in the HACCR register to 1. The HAC then
transmits the data to the codec via slot 2.
After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received
via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related
codec register address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯
Bit:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value:
R R R R R R R R R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R R R R
R/W:
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
CD11/
SD11
CD10/
SD10
CD9/
SD9
CD8/
SD8
CD7/
SD7
CD6/
SD6
CD5/
SD5
CD4/
SD4
CD3/
SD3
CD2/
SD2
CD1/
SD1
CD0/
SD0
CD15/
SD15
CD14/
SD14
CD13/
SD13
CD12/
SD12
0