Renesas SH7781 User Manual

Page 146

5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 116 of 1658
REJ09B0261-0100

(11)

General FPU Disable Exception

• Source: Decoding of an FPU instruction* not in a delay slot with SR.FD = 1
• Transition address: VBR + H'00000100
• Transition operations:

The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.

Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.

Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F

(but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L
instructions corresponding to FPUL and FPSCR.

General_fpu_disable_exception()

{

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'0000 0800;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'0000 0100;

}