Renesas SH7781 - Manual (Page 760)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 730 of 1658
REJ09B0261-0100
14.6 Usage Notes
Note the following things in using this DMAC.
14.6.1 Stopping Modules and Changing Frequency
When the DMAC is operating, it is prohibited to set or clear the corresponding bit of MSTPCR1
that controls H-UDI, UBC, DMAC and GDTA modules operation, and also prohibited to change
any frequencies regarding the operation of this LSI. Operation is not guaranteed if these are
performed.
Check that the DME bits (bit 0) in both DMAOR0 and DMAOR1 are 0 or the TE bits in CHCR0
to CHCR11 are all 1 before stopping modules by MSTPCR1.
14.6.2 Address Error
When a DMA address error is occurred, set registers of all channels of corresponding DMAOR*
again and then start a transfer.
Note: Set registers of channels 0 to 5 again when the AE bit of DMAOR0 is set to 1, and set
registers of channels 6 to 11 again when the AE bit of DMAOR1 is set to 1.
14.6.3 NMI Interrupt
When a NMI interrupt is occurred, DMA transfer is stopped. Set registers of all channels again
after returning from the exception handling routine of a NMI and then start a transfer.
14.6.4 Burst Mode Transfer
During a burst mode transfer, do not make a transition to sleep mode until the transfer of
corresponding channel has been completed.
14.6.5 Divided-Up DACK Output
When 16- or 32-byte transfer is performed in 8-, 16-, 32-, or 64-bit bus width, longword transfer is
performed in 8- or 16-bit bus width, or word transfer is performed in 8-bit bus width, DMA
transfer units are divided into multiple bus cycles. Note that DACK output is divided-up, like CS,
if DMA transfer size is divided into multiple bus cycles and CS is negated between bus cycles.