Renesas SH7781 - Manual (Page 1563)

31. Register List
Rev.1.00 Jan. 10, 2008 Page 1533 of 1658
REJ09B0261-0100
31.2 States of the Registers in the Individual Operating Modes
The states of the I/O registers incorporated in the SH7785 in the individual operating modes are
listed in tables 31.2 to table 31.9. The registers are described in order of section number in this
manual, and are grouped by functional module. Since this is a summary, parts of the descriptions,
along with the notes, have been omitted. For details on the registers, refer to the descriptions in the
corresponding sections.
Table 31.2 States of the Registers in the Individual Operating Modes (1)
Module
Name Name Abbrev.
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Manual Reset
by
WDT/Multiple
Exception
Sleep/
Deep Sleep by
SLEEP
Instruction
TRAPA exception register TRA Undefined Undefined Retained Exception
processing
Exception event register EXPEVT H'0000 0000 H'0000 0020 Retained
Interrupt event register INTEVT Undefined Undefined Retained
Non-support detection exception register EXPMASK H'0000 0013 H'0000 0013 Retained
MMU Page table entry high register PTEH Undefined Undefined Retained
Page table entry low register PTEL Undefined Undefined Retained
Translation table base register TTB Undefined Undefined Retained
TLB exception address register TEA Undefined Retained Retained
MMU control register MMUCR H'0000 0000 H'0000 0000 Retained
Physical address space control register PASCR H'0000 0000 H'0000 0000 Retained
Instruction re-fetch inhibit control register IRMCR H'0000 0000 H'0000 0000 Retained
Page table entry assistance register PTEA Undefined Undefined Retained
Cache Cache control register CCR H'0000 0000 H'0000 0000 Retained
Queue address control register 0 QACR0 Undefined Undefined Retained
Queue address control register 1 QACR1 Undefined Undefined Retained
On-chip memory control register RAMCR H'0000 0000 H'0000 0000 Retained
L memory L memory transfer source address register 0 LSA0 Undefined Undefined Retained
L memory transfer source address register 1 LSA1 Undefined Undefined Retained
L memory transfer destination address
register 0
LDA0 Undefined Undefined Retained
L memory transfer destination address
register 1
LDA1 Undefined Undefined Retained