Renesas SH7781 - Manual (Page 86)

3. Instruction Set
Rev.1.00 Jan. 10, 2008 Page 56 of 1658
REJ09B0261-0100
Instruction Operation Instruction Code Privileged T Bit New
CMP/STR Rm,Rn When any bytes are equal,
1
→ T
Otherwise, 0
→ T
0010nnnnmmmm1100 — Comparison
result
—
DIV1 Rm,Rn 1-step division (Rn
÷ Rm) 0011nnnnmmmm0100 — Calculation
result
—
DIV0S Rm,Rn MSB of Rn → Q,
MSB of Rm → M, M^Q →
T
0010nnnnmmmm0111 — Calculation
result
—
DIV0U 0
→ M/Q/T
0000000000011001 — 0 —
DMULS.L Rm,Rn Signed,
Rn × Rm → MAC,
32 × 32 → 64 bits
0011nnnnmmmm1101 — — —
DMULU.L Rm,Rn Unsigned,
Rn
× Rm → MAC,
32
× 32 → 64 bits
0011nnnnmmmm0101 — — —
DT Rn Rn – 1
→ Rn;
when Rn = 0, 1
→ T
When Rn
≠ 0, 0 → T
0100nnnn00010000 — Comparison
result
—
EXTS.B Rm,Rn Rm sign-extended from
byte
→ Rn
0110nnnnmmmm1110 — — —
EXTS.W Rm,Rn Rm sign-extended from
word
→ Rn
0110nnnnmmmm1111 — — —
EXTU.B Rm,Rn Rm zero-extended from
byte
→ Rn
0110nnnnmmmm1100 — — —
EXTU.W Rm,Rn Rm zero-extended from
word
→ Rn
0110nnnnmmmm1101 — — —
MAC.L @Rm+,@Rn+ Signed,
(Rn)
× (Rm) + MAC →
MAC
Rn + 4
→ Rn, Rm + 4 →
Rm
32
× 32 + 64 → 64 bits
0000nnnnmmmm1111 — — —
MAC.W @Rm+,@Rn+ Signed,
(Rn)
× (Rm) + MAC →
MAC
Rn + 2
→ Rn,
Rm + 2
→ Rm
16
× 16 + 64 → 64 bits
0100nnnnmmmm1111 — — —
MUL.L Rm,Rn Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111 — — —
MULS.W Rm,Rn Signed,
Rn
× Rm → MACL
16
× 16 → 32 bits
0010nnnnmmmm1111 — — —