Renesas SH7781 - Manual (Page 408)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 378 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
27
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
26 to 24 ADH 111 R/W Address Hold Cycle
These bits specify the number of cycles to be inserted
as the address hold time with respect to
CSn negation.
(Only valid when the SRAM interface, byte control
SRAM interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
23
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
22 to 20 RDS 111 R/W
RD Setup Cycle (CSn Assertion–RD Assertion Delay
Cycle)
These bits specify the number of cycles to be inserted
as the time from
CSn assertion to RD assertion. (Only
valid only when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted (1 cycle delayed)
001: 1 cycle inserted (2 cycles delayed)
010: 2 cycles inserted (3 cycles delayed)
011: 3 cycles inserted (4 cycles delayed)
100: 4 cycles inserted (5 cycles delayed)
101: 5 cycles inserted (6 cycles delayed)
110: 6 cycles inserted (7 cycles delayed)
111: 7 cycles inserted (8 cycles delayed)