Renesas SH7781 - Manual (Page 1521)

30. User Debugging Interface (H-UDI)
Rev.1.00 Jan. 10, 2008 Page 1491 of 1658
REJ09B0261-0100
30.3 Register Description
The H-UDI has the following registers.
Table 30.2 Register Configuration (1)
CPU Side
Register Name Abbreviation R/W Area P4 Address Area 7 Address Size
Sync
Clock
Instruction register SDIR R H'FC11 0000 H'1C11 0000 16 Pck
Interrupt source register SDINT R/W H'FC11 0018 H'1C11 0018 16 Pck
Boundary scan register SDBSR ⎯ ⎯ ⎯ ⎯ ⎯
Bypass register SDBPR
⎯ ⎯ ⎯ ⎯ ⎯
Table 30.3 Register Configuration (2)
H-UDI Side
Register Name Abbreviation R/W Size Sync Clock
Instruction register SDIR R/W* 1 32 Pck
Interrupt source register SDINT W* 2 32 Pck
Boundary scan register SDBSR R/W
⎯ ⎯
Bypass register SDBPR R/W 1 ⎯
Notes: 1. The read value from the H-UDI is always fixed to H’FFFF FFFD.
2. 1 can be written to the LSB by the H-UDI interrupt command.
Table 30.4 Register States in Each Processing State
Register Name Abbreviation
Power-On
Reset Manual
Reset Module
Standby Sleep Deep
Sleep
Instruction register SDIR H'0EFF Retained Retained Retained Retained
Interrupt source
register SDINT H'0000 Retained Retained Retained Retained