Renesas SH7781 - Manual (Page 793)

16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 763 of 1658
REJ09B0261-0100
16.3.1 Watchdog Timer Stop Time Register (WDTST)
WDTST is a 32-bit readable/writable register that specifies the time until watchdog timer counter
WDTCNT overflows. The time until WDTCNT overflows becomes minimum when H'5A00 0001
is set, and maximum when H'5A00 0000 is set.
WDTST should be written as a longword unit, with H'5A in the most significant byte. The value
read from this byte is always H'00. WDTST is only rest by a power-on reset caused by the
PRESET pin.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
Code for writing (H'5A)
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDTST ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 24 (Code for
writing)
All 0 R/W Code for writing (H'5A)
These bits are always read as H'00. When writing to
this register, the value written to these bits must be
H'5A.
23 to 12
⎯ All
0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 WDTST All 0 R/W Timer Stop
These bits set the counter value at which WDTCNT
overflows.
H'001: Minimum overflow value
H'000: Maximum overflow value