Renesas SH7781 - Manual (Page 1368)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1338 of 1658
REJ09B0261-0100
(5) Data Transfer FIFO
• On-chip 224-byte FLDTFIFO for data transfer of flash memory
• On-chip 32-byte FLECFIFO for data transfer of a control code
• Flag bit for detection of overrun or underrun during access from the CPU or DMA
(6)
DMA Transfer
• By individually specifying the transfer destinations of data and control code of flash memory
to the DMA controller, data and control code can be transferred to different areas.
(7) Access Size
• Registers include 32-bit registers and an 8-bit register. Read from or write to the register with
the specified access size.
• The access size of FIFO is 32 bits (4 bytes). In reading, set the byte number to a multiple of
four. In writing, set the byte number to a multiple of four in writing.
(8)
Access Time
• The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the
QTSEL bit in FLCMNCR, regardless of the operating frequency of the peripheral bus.
• The operating clock, FCLK, on the pins for the NAND-type flash memory is used by dividing
the operating clock of the peripheral bus (a peripheral clock).
• In NAND-type flash memory, the FRE and FWE pins operate with the FCLK specified by
FLCMNCR. To ensure the setup time, this operating frequencies should not exceed the
maximum operating frequency of memory to be connected.