Renesas SH7781 - Manual (Page 595)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 565 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value
R/W Description
6 PER 0 SH: R/W
PCI: R/W
Parity Error Response
Controls the response of the device when the PCIC
detects a parity error or receives a parity error. When
this bit is set to 1, the
PERR signal is asserted.
0: Ignores parity error
1: Responds to parity error
5 VGAPS 0 SH: R
PCI: R
VGA Palette Snoop Control
0: VGA compatible device
1: Incompatible with palette register write (not
supported)
4 MWIE 0 SH: R
PCI: R
Memory Write and Invalidate Control
This bit controls issue of a memory and invalidate
command when the PCIC is a master.
0: Memory write is used
1: Memory write and invalidate command can be
executed (not supported)
3 SC 0 SH: R
PCI: R
Special Cycle Control
This bit indicates whether special cycles are supported
when the PCIC is a target.
0: Special cycles ignored
1: Special cycles monitored (not supported)
2 BM 0 SH: R/W
PCI: R/W
PCI Bus Master Control
Controls a bus master.
0: Bus master disabled
1: Bus master enabled
1 MS 0 SH: R/W
PCI: R/W
PCI Memory Space Control
This bit controls accesses to memory spaces when the
PCIC is a target. When this bit is cleared to 0, a
memory transfer to the PCIC is completed by master
abort.
0: Accesses to memory spaces disabled
1: Accesses to memory spaces enabled
0 IOS 0 SH: R/W
PCI: R/W
PCI I/O Space Control
This bit controls accesses to memory spaces when the
PCIC is a target. When this bit is cleared to 0, an I/O
transfer to the PCIC is completed by master abort.
0: Accesses to I/O spaces disabled
1: Accesses to I/O spaces enabled