Renesas SH7781 - Manual (Page 545)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 515 of 1658
REJ09B0261-0100
command to be issued at time 2 from the following request queue. From the search results it is
seen that advance precharge processing can be executed for the third read (8-byte) request and the
fourth read (16-byte) request. Because the DBSC2 gives priority to preceding requests, it decides
to perform advance precharge processing for the third read (8-byte) request, and issues a PRE
command to the SDRAM.
When the time advances to time 3, the ACT command cannot be issued for the first read (16-byte)
request at time 3 either, and so a search of the following queue is performed for a command which
can be issued. Due to timing constraints, the ACT command cannot be issued for the third read (8-
byte) request, and as a result, issuance of the PRE command corresponding to the fourth read (16-
byte) request is selected.
At time 4, it is possible to execute request processing for the first read (16-byte) request, and an
ACT command is issued to the DDR2-SDRAM.
Thereafter, the processing described above is repeated.
Request
No.
1
2
3
4
SDRAM command
Request
Read (16 bytes)
Read (32 bytes)
Read (8 bytes)
Read (16 bytes)
Bank to be
accessed
Bank 0
Bank 1
Bank 2
Bank 3
Page state
during request
Miss
Hit
Miss
Miss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PRE
PRE PRE PRE ACT ACT READ ACT READ READ READ READ
PRE
PRE
ACT
ACT
READ
READ READ
READ
READ
Time Time Time Time Time Time Time Time Time Time Time Time Time Time Time
As the burst length is 4 in the DDR2-SDRAM, the interval between READ commands is always two cycles.
ACT
Figure 12.6 Example of Preceding Precharge/Activate Processing