Renesas SH7781 - Manual (Page 406)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 376 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value
R/W Description
6 to 4 BW 111 R/W Burst Pitch
When the burst ROM interface is used, these bits
specify the number of wait cycles to be inserted after
the second data access in a burst transfer.
000: No idle cycle inserted,
RDY pin disabled
001: 1 idle cycle inserted,
RDY pin enabled
010: 2 idle cycles inserted,
RDY pin enabled
011: 3 idle cycles inserted,
RDY pin enabled
100: 4 idle cycles inserted,
RDY pin enabled
101: 5 idle cycles inserted,
RDY pin enabled
110: 6 idle cycles inserted,
RDY pin enabled
111: 7 idle cycles inserted,
RDY pin enabled
3 MPX 0 R/W* MPX Interface Setting
Selects the type of the MPX interface
0: Memory type set by bits TYPE2 to TYPE0 is selected
1: MPX interface is selected
Note: * The MPX bit in CS0BCR is read-only.
2 to 0 TYPE 000 R/W Memory Type Setting
These bits specify the type of memory connected to the
space.
000: SRAM (Initial value)
001: SRAM with byte-control* 1
010: Burst ROM (burst at read/SRAM at write)
011: Reserved (Setting prohibited)
100: PCMCIA * 2
101: Reserved (Setting prohibited)
110: Reserved (Setting prohibited)
111: Reserved (Setting prohibited)
Notes: 1. Setting enabled only in CS1BCR and
CS4BCR
2. Setting enabled only in CS5BCR and
CS6BCR