Renesas SH7781 - Manual (Page 124)

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 94 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
31 to 5
⎯ All
0 R Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
4 MMCAW 1 R/W Memory-Mapped Cache Associative Write
0: Memory-mapped cache associative write is disabled.
(A data address error exception will occur.)
1: Memory-mapped cache associative write is enabled.
For further details, refer to section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
3, 2
⎯ All
0 R Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
1 BRDSSLP 1 R/W Delay Slot SLEEP Instruction
0: The SLEEP instruction in the delay slot is disabled.
(The SLEEP instruction is taken as a slot illegal
instruction.)
1: The SLEEP instruction in the delay slot is enabled.
0 RTEDS 1 R/W RTE Delay Slot
0: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is disabled. (An
instruction other than the NOP instruction is taken as
a slot illegal instruction).
1: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is enabled.