Renesas SH7781 - Manual (Page 773)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 743 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
31
30
29
28
IFC3
IFC2
IFC1
IFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the CPU clock (Ick)
0000: No change
0001:
Ч 1/2
0010:
Ч 1/4
0011:
Ч 1/6
Others: Setting prohibited
27
26
25
24
UFC3
UFC2
UFC1
UFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the RAM clock (Uck)
0000: No change
0010:
Ч 1/4
0011:
Ч 1/6
Others: Setting prohibited
23
22
21
20
SFC3
SFC2
SFC1
SFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the SuperHyway clock
(SHck)
0000: No change
0010:
Ч 1/4
0011:
Ч 1/6
Others: Setting prohibited
19
18
17
16
BFC3
BFC2
BFC1
BFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the bus clock (Bck)
0000: No change
0101:
Ч 1/12
0110:
Ч 1/16
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48
Others: Setting prohibited
15
14
13
12
MFC3
MFC2
MFC1
MFC0
0
0
0
0
R/W
R/W
R/W
R/W
Frequency division ratio of the DDR clock (DDRck)
0000: No change
0010:
Ч 1/4
0011:
Ч 1/6
Others: Setting prohibited