Renesas SH7781 - Manual (Page 1294)

25. Audio Codec Interface (HAC)
Rev.1.00 Jan. 10, 2008 Page 1264 of 1658
REJ09B0261-0100
Figure 25.1 shows a block diagram of the HAC.
HAC receiver
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
Internal bus interface (Reception)
CSAR RX buffer
CSDR RX buffer
PCML RX buffer
PCMR RX buffer
DMA control
DMA request
Interrupt request
Internal bus interface (Transmission)
CSAR TX buffer
CSDR TX buffer
PCML TX buffer
PCMR TX buffer
DMA control
HAC transmitter
Shift register for slot 1
Shift register for slot 2
Shift register for slot 3
Shift register for slot 4
DMA request
Data[19:0]
Data[19:0]
Data[31:0]
Data[31:0]
Data[19:0]
Data[19:0]
Control signal
Bit control signal
Interrupt request
Data[19:0]
Data[19:0]
Data[19:0]
Data[19:0]
Control signal
P
er
ipher
al b
us
Request signal
for slots 3 and 4
HACn_SDIN
HACn_BITCLK
HACn_SDOUT
HACn_SYNC
HACn_RES
Note: n = 0 to 1
Figure 25.1 Block Diagram