Renesas SH7781 - Manual (Page 1238)

24. Multimedia Card Interface (MMCIF)
Rev.1.00 Jan. 10, 2008 Page 1208 of 1658
REJ09B0261-0100
24.3.18 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal.
The DMA request signal is output based on a value that has been set to SET2 to SET0.
Bit:
Initial value:
R/W:
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W
DMAEN SET2 SET1 SET0
R/W R R R R/W R/W R/W
AUTO ⎯ ⎯ ⎯
Bit Bit Name
Initial
Value R/W Description
7 DMAEN 0 R/W DMA Enable
0: Disables output of DMA request signal.
1: Enables output of DMA request signal.
6 AUTO 0 R/W Auto Mode for pre-define multiple block transfer using
DMA transfer
0: Disable auto mode
1: Enable auto mode
5 to 3
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
2
1
0
SET2
SET1
SET0
0
0
0
R/W
R/W
R/W
DMA Request Signal Assert Condition
Sets DMA request signal assert condition.
000: Not output
001: FIFO remained data is 1/4 or less of FIFO capacity.
010: FIFO remained data is 1/2 or less of FIFO capacity.
011: FIFO remained data is 3/4 or less of FIFO capacity.
100: FIFO remained data is 1 byte or more.
101: FIFO remained data is 1/4 or more of FIFO capacity.
110: FIFO remained data is 1/2 or more of FIFO capacity.
111: FIFO remained data is 3/4 or more of FIFO capacity.