Renesas SH7781 - Manual (Page 1076)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1046 of 1658
REJ09B0261-0100
21.3.1 Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting
with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to SCFRDR, automatically.
SCRSR cannot be directly read from and written to by the CPU.
0 1 2 3 4 5 6 7
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W:
21.3.2 Receive FIFO Data Register (SCFRDR)
SCFRDR is an 8-bit FIFO register of 64 stages that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until SCFRDR is full.
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in SCFRDR, an undefined value is returned.
When SCFRDR is full of receive data, subsequent serial data is lost.
0 1 2 3 4 5 6 7
R R R R R R R R
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W: