Renesas SH7781 - Manual (Page 103)

4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 73 of 1658
REJ09B0261-0100
I1 I2 I3 ID s1 s2 s3
s1 s2 s3 WB
s1 s2 s3 WB
FS1 FS2 FS3 FS4
FS1 FS2 FS3 FS4
FS
FS1 FS2 FS3 FS4
FS1 FS2 FS3 FS4
FS1 FS2 FS3 FS4
FS
FS1 FS2 FS3 FS4 FS
FS1 FS2 FS3 FS4
FS1 FS2 FS3 FS4
FS
FS1 FS2 FS3 FS4 FS
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I1 I2 ID
I1 I2 ID S1 S2 S3 WB
S1 S2 S3
S1 S2 S3
WB
I1 I2 ID s1 s2 s3
I1 I2 ID WB
S1 S2 S3 WB
FS1 FS2 FS3 FS4
S1 S2 S3 WB
FS1 FS2 FS3 FS4 FS
s1 s2 s3 WB
I1 I2 ID
I1 I2 ID
I1 I2 ID
I1 I2 ID
I1 I2 ID
I1 I2 ID
s1 s2 s3
FS
(6-1) LDS to FPUL: 1 issue cycle
(6-2) STS from FPUL: 1 issue cycle
(6-3) LDS.L to FPUL: 1 issue cycle
(6-4) STS.L from FPUL: 1 issue cycle
(6-5) LDS to FPSCR: 1 issue cycle
(6-6) STS from FPSCR: 1 issue cycle
(6-7) LDS.L to FPSCR: 1 issue cycle
(6-8) STS.L from FPSCR: 1 issue cycle
(6-9) FPU load/store instruction FMOV: 1 issue cycle
(6-10) FLDS: 1 issue cycle
(6-11) FSTS: 1 issue cycle
Figure 4.2 Instruction Execution Patterns (7)