Renesas SH7781 User Manual
Page 16
Rev.1.00 Jan. 10, 2008 Page xvi of xxx
REJ09B0261-0100
12.5.11
Method for Securing Time Required for Initialization, Self-Refresh
Cancellation, etc. ................................................................................................ 549
12.5.12
Regarding the Supported Clock Ratio ................................................................ 549
12.5.13
Regarding MCKE Signal Operation ................................................................... 550
Section 13 PCI Controller (PCIC)
................................................................................... 551
13.1
Features.............................................................................................................................. 551
13.2
Input/Output Pins............................................................................................................... 554
13.3
Register Descriptions ......................................................................................................... 557
13.3.1
PCIC Enable Control Register (PCIECR) .......................................................... 562
13.3.2
Configuration Registers ...................................................................................... 563
13.3.3
PCI Local Registers ............................................................................................ 590
13.4
Operation ........................................................................................................................... 630
13.4.1
Supported PCI Commands ................................................................................. 630
13.4.2
PCIC Initialization .............................................................................................. 631
13.4.3
Master Access..................................................................................................... 632
13.4.4
Target Access ..................................................................................................... 640
13.4.5
Host Mode .......................................................................................................... 648
13.4.6
Normal Mode...................................................................................................... 651
13.4.7
Power Management ............................................................................................ 651
13.4.8
PCI Local Bus Basic Interface............................................................................ 653
Section 14 Direct Memory Access Controller (DMAC)
........................................... 665
14.1
Features.............................................................................................................................. 665
14.2
Input/Output Pins............................................................................................................... 667
14.3
Register Descriptions ......................................................................................................... 668
14.3.1
DMA Source Address Registers 0 to 11 (SAR0 to SAR11) ............................... 675
14.3.2
DMA Source Address Registers B0 to B3, B6 to B9
(SARB0 to SARB3, SARB6 to SARB9)............................................................ 676
14.3.3
DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ...................... 677
14.3.4
DMA Destination Address Registers B0 to B3, B6 to B9
(DARB0 to DARB3, DARB6 to DARB9) ......................................................... 678
14.3.5
DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)................................ 679
14.3.6
DMA Transfer Count Registers B0 to B3, B6 to B9
(TCRB0 to TCRB3, TCRB6 to TCRB9)............................................................ 680
14.3.7
DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ....................... 681
14.3.8
DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) ................................ 689
14.3.9
DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)................. 693
14.4
Operation ........................................................................................................................... 701
14.4.1
DMA Transfer Requests ..................................................................................... 701