Renesas SH7781 - Manual (Page 1008)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 978 of 1658
REJ09B0261-0100
Table 20.6 GDTA States in Each Processing Mode (MC Block)
Register
Abbreviation Power-On
Reset
Manual Reset Sleep Deep Sleep
Module
Standby
MCCF H'0000 0000 H'0000 0000 Retained H'0000_0000 H'0000_0000
MCSR H'0000 0000 H'0000 0000 Retained Retained Retained
MCWR H'0000 0000 H'0000 0000 Retained Retained Retained
MCHR H'0000 0000 H'0000 0000 Retained Retained Retained
MCYPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCUVPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCOYPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCOUPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCOVPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCPYPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCPUPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCPVPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCFYPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCFUPR H'0000 0000 H'0000 0000 Retained Retained Retained
MCFVPR H'0000 0000 H'0000 0000 Retained Retained Retained
Note: A 0 is always read from these registers.