Renesas SH7781 - Manual (Page 324)

10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 294 of 1658
REJ09B0261-0100
Bit Name
Initial
Value R/W Description
23 IC007 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HLLL (H'8).
22 IC006 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HLLH (H'9).
21 IC005 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HLHL (H'A).
20 IC004 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HLHH (H'B).
19 IC003 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HHLL (H'C).
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
18 IC002 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HHLH (H'D).
17 IC001 0 R/W Clears masking of the
interrupt source of
IRL3 to
IRL0 = HHHL (H'E).
16 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
15 IC115 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LLLL (H'0).
14 IC114 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LLLH (H'1).
13 IC113 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LLHL (H'2).
12 IC112 0 R/W Clears masking of the
interrupt source of
IRL7 to
IRL4 = LLHH (H'3).
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)