Renesas SH7781 - Manual (Page 665)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 635 of 1658
REJ09B0261-0100
For PCI memory space 2 accesses, the middle eleven bits ([28:18]) are controlled by PCIMBMR2.
• PCIMBMR2 [28:18] B'1 1111 1111 11: PCI address [28:18] = SuperHyway bus address [28:18]
• PCIMBMR2 [28:18] B'0 0000 0000 00: PCI address [28:18] = PCIMBR2 [28:18]
The upper three bits ([31:29]) of a SuperHyway bus address are replaced with bits 31 to 29 in
PCIMBR2.
SHwy bus address PCI address
PCIMBMR2
PCIMBR2
mask
31 29 28 18 17 0
31 29 28 18 17 0
31 29 28 18 17 0
31 29 28 18 17 0
Figure 13.5 Access from SuperHyway Bus to PCI Memory (PCI Bus)
(PCI Memory Space 2)