Renesas SH7781 - Manual (Page 1619)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1589 of 1658
REJ09B0261-0100
D31 to D0
(2) 1st data: One internal wait cycle, 2nd to 8th data: No internal wait + external wait control
Information in the first data bus cycle
D31 to D29:
Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
D31 to D0
(1) No internal wait
Information in the first data bus cycle
D31 to D29:
Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
Legend:
IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
Tm1
CLKOUT
RD/FRAME
CSn
RD/ WR
RDY
BS
DACKn
(DA)
CLKOUT
RD/FRAME
CSn
RD/ WR
RDY
BS
DACKn
(DA)
t
FMD
Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8
A D1 D2 D3 D4 D5 D6 D7 D8
t
FMD
t
WDD
t CSD t CSD
t
RWD
t RDYS t RDYH
t
RWD
t DACD t DACD
t
WDD
t
WDD
t
BSD
t
BSD
Tm1
t
FMD
Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8
A D1 D2 D8 D3 D7
t
FMD
t WDD
t
CSD
t
CSD
t RWD
t
RDYS
t
RDYH
t RWD
t
DACD
t
DACD
t WDD
t
BSD
t
BSD
t WDD
t
RDYS
t
RDYH
Figure 32.23 MPX Bus Cycle (Burst Write)